In the field of nonvolatile semiconductor memories of the metal nitride oxide semiconductor field effect transistor (MNOS FET) type, binary information is stored in the memory transistors of an array by appropriately switching the threshold voltages of the memory transistors between their upper and lower stable states. To enable the sensing of the memory transistors' present state, or the analog voltage characteristic of each memory transistor's stable states, a sense latch is coupled to the memory array. Such a sense latch was previously described in the earlier filed patent applications of Merton A. Horne and Thomas A. Pogemiller, Ser. No. 821,272, filed Aug. 3, 1977; and Bruce A. Brillhart and Merton A. Horne, Ser. No. 821,271, filed Aug. 3, 1977. The sense latch of the earlier applications described a sense latch circuit and the method for operating the sense latch in its various modes of operation in a random access memory (RAM), where the threshold voltages, corresponding to the binary information stored in the associative MNOS memory cells, were indirectly sensed and used to switch the gates of transistors selectively coupled in parallel to the sense latch.
Due to the organizational differences between the previous RAM organization and the BORAM organization described herein, it becomes prohibitive from the standpoint of the amount of space available on an integrated circuit chip to implement the earlier defined circuitry in an unmultiplexed BORAM. The present invention therefore teaches a sense amplifier/latch circuit which provides for the direct sensing of the memory transistors' threshold voltages by incorporating the memory transistors in the sense latch and impressing an appropriate row address voltage on the gates of the memory transistors for sensing the corresponding stored binary information and the analog threshold voltage memory window for each column of associative memory cells of the BORAM. While an equal number of sense amplifier/latch circuits as the number of columns in the memory array are required in the present BORAM organization, the different sensing technique and improved sense latch circuitry minimize the amount of chip space required and improve the switching speed of the sense latch, thereby making it possible to test the characteristic threshold voltages of the memory transistors but for a memory array of eight times the size as previously described.
In a paper, entitled Hardened MNOS/SOS Electrically Reprogammable Non-Volatile Memory, authored by J. R. Cricchi, et al, of Westinghouse Electric Corp. and B. T. Ahlport of Northrop Corp., delivered to the IEEE Annual Conference on Nuclear and Space Radiation Effects on July 12 to 15, 1977, a sense latch circuit and technique is disclosed for use in conjunction with an electrically reprogrammable MNOS RAM memory which is fabricated on a sapphire substrate. The RAM is organized in a 64 .times. 16 array, which is multiplexed to produce a 256-word .times. 4-bit MNOS/SOS memory. The sense latch used in conjunction with this organization, while similar in basic appearance to the present invention, inherently contains significant differences which preclude its use in BORAM organizations similar to that taught by the present invention. Its application in an unmultiplexed BORAM organization, similar to that described herein, would require additional chip space to accommodate the test point transistors as well as an additional 64 pins per chip to enable the measurement of the chip's analog memory window. The significance of these differences are more fully described hereinafter.
The sense amplifier/latch of the present invention therefore teaches an improved sense latch operable in selective read, write and analog threshold test modes of operation, which can be efficiently incorporated in a BORAM organization without a burdensome increase in the total number of external pins or in the chip size.